`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:26:45 07/08/2015 
// Design Name: 
// Module Name:    LatchIFID 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module LatchIFID(
	input [31:0] InstruccionIn,
	input [31:0] E1AdderIn,
	input clk,
	input stallone,
	output reg [31:0] InstruccionOut,
	output reg [31:0] E1AdderOut
    );

always@(negedge clk) begin
	if(!stallone) begin
		InstruccionOut = InstruccionIn;
		E1AdderOut = E1AdderIn;
	end
end

endmodule
